This invention relates to a power semiconductor circuit comprising an insulated gate field effect power semiconductor device and a gate control circuit for controlling the application of voltages to the insulated gate electrode of the power semiconductor device.
U.S. Pat. No. 4,928,053 describes a power semiconductor device circuit in which the power semiconductor device is an n-channel power MOSFET intended to be used as a high-side switch for an inductive load. As will be understood by those skilled in the art, a `high-side switch` in the case of an n-channel device is a switch which is coupled between the load and the more positive of the two voltage supply lines. In the circuit described in U.S. Pat. No. 4,928,053, a voltage clamping circuit in the form of a zener diode is coupled between the positive voltage supply terminal, to which one main electrode of the power semiconductor device is coupled, and the gate electrode of the power semiconductor device. The main current path, that is the current path between its main electrodes, of an n-channel MOS transistor is coupled between the gate and the other main electrode of the power semiconductor device. The gate electrode of the n-channel MOST is coupled together with the gate electrode of a p-channel MOST to the other supply line which is, as shown, at ground. The main current path of the p-channel MOS transistor is coupled between the gate electrode of the power MOSFET and a gate drive circuit. In the operation of the circuit described in U.S. Pat. No. 4,928,053 when an overvoltage occurs due to the switching of the inductive load, the zener diode breaks down and the n-channel MOS transistor provides a conduction path, bypassing the power semiconductor device, for dissipation of the energy in the inductive load. At the same time, the p-channel MOS is switched off thereby isolating the power MOSFET from the gate drive circuit.